View HT25LC512_286493.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HT25LC512
CMOS 64K8-Bit SPI Serial OTP EPROM
Features
* Operating voltage: 2.7V~3.6V * Programming voltage - VPP=12.5V0.2V - VCC=6.0V0.2V * 512K-bit OTP ROM, access command compatible * Serial interface architecture * Serial Peripheral Interface (SPI) compatible - modes
0 and 3
* CMOS and TTL compatible inputs and outputs * Pin assignment compatible with AT25F512 * Commercial temperature range (0C to +70C) * 8-pin SOP package
with AT25F512
* 64K8-bit organization * 12MHz max. clock frequency @VCC=2.7V
15MHz max. clock frequency @VCC=3.0V
General Description
The HT25LC512 is a 512K-bit OTP ROM of which function and pin assignment are compatible with AT25F512 and can directly replace the AT25F512 for cost down purposes when the memory in the system is just read only. There are 512K bits of memory which are organized as 65536 words of 8 bits each. The HT25LC512 uses a serial interface to sequentially access its data. The simple serial interface facilitates hardware layout, increase system reliability, minimize switching noise, and reduce package size and active pin count. The device is optimized for use in many commercial and industrial applications where high density, low pin count, low voltage, and low power consumption are essential. The device operates at clock frequencies up to 10MHZ. The HT25LC512 is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK). The HOLD pin may be used to suspend any serial communication without resetting the serial sequence.
Block Diagram
SCK HO LD C lo c k G e n e ra to r SC LK SI CS S IP O R e g is te r VPP X -a d d r SC LK SI CS S ta te C o n tro l Y -a d d r CE OE O u tp u t MUX ID R e g is te r OTP ROM S ta tu s R e g is te r
SC LK CS
P IS O R e g is te r
SO
Rev. 1.00
1
June 14, 2004
HT25LC512
Pin Assignment
CS 1 8 2 7 3 6 4 5 SO VPP GND VCC HO LD SCK SI
H T25LC 512 8 S O P -A
Pin Description
Pin No. 1 2 3 4 5 6 7 8 Pin Name CS SO VPP GND SI SCK HOLD VCC Chip select Serial Output Program voltage supply Negative power supply, ground Serial input Serial clock Suspends serial input Positive power supply Description
Absolute Maximum Rating
Operation Temperature Commercial ..........................................................................................................0C to +70C Storage Temperature.............................................................................................................................-65C to 125 C Applied VCC Voltage with Respect to VSS ................................................................................................-0.6V to 7.0V Applied Voltage on Input Pin with Respect to VSS .....................................................................................-0.6V to 7.0V Applied Voltage on Output Pin with Respect to VSS ......................................................................... -0.6V to VCC+0.5V Applied VPP Voltage with Respect to VSS...............................................................................................-0.6V to 13.5V Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol Read operation VCC VIL VIH VOL VOH Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 3/4 3/4 3/4 3/4 3/4 3/4 2.7 -0.5 0.7VCC 3/4 VCC-0.2 3/4 3/4 3/4 3/4 3/4 Parameter Test Conditions VCC Conditions Min. Typ.
Ta=0C to +70C Max. Unit
3.6 0.2VCC VCC+0.5 0.2 3/4
V V V V V
2.7V~ IOL=0.15mA; 3.6V 2.7V VCC 3.6V 2.7V~ IOH=-100mA 3.6V
Rev. 1.00
2
June 14, 2004
HT25LC512
Symbol ISTB ICC IIL IOL Parameter Test Conditions VCC Conditions Min. 3/4 3/4 -3 -3 Typ. Max. Unit mA mA mA mA
Standby Current Active Current, Read Operation Input Leakage Current Output Leakage Current
2.7V~ CS=VCC=3.6V, all in3.6V puts at CMOS levels 2.7V~ f=10MHz; SO=open 3.6V VCC=3.6V 2.7V~ VIN=0V to VCC 3.6V 2.7V~ VIN=0V to VCC 3.6V
2 10 3/4 3/4
10 15 3 3
Programming operation VCC VPP VIL VIH Note: Supply Voltage Supply Voltage Input Low Voltage Input High Voltage 3/4 3/4 6.0V 6.0V 3/4 3/4 3/4 3/4 5.8 12.3 -0.5 0.7VCC 6.0 12.5 3/4 3/4 6.2 12.7 0.2VCC VCC+0.5 V V V V
VPP overshoot/undershoot riaging caused by fast rising time must not go below 11V or above 13V. Ta=0C to +70C, VCC=2.7V to 3.6V Test Conditions VCC=2.7V~3.0V VCC=3.0V~3.6V SCK High Time VCC=2.7V~3.0V VCC=3.0V~3.6V SCK Low Time Minimum CS High Time CS Setup Time CS Hold Time Data in Setup Time Data in Hold Time HOLD Setup Time HOLD Hold Time Output Hold Time Output Disable Time Output Valid HOLD to Output Low Z HOLD to Output High Z VCC=2.7V~3.0V VCC=3.0V~3.6V VCC=2.7V~3.6V VCC=2.7V~3.6V VCC=2.7V~3.6V VCC=2.7V~3.6V VCC=2.7V~3.6V VCC=2.7V~3.6V VCC=2.7V~3.6V VCC=2.7V~3.6V VCC=2.7V~3.6V VCC=2.7V~3.0V VCC=3.0V~3.6V VCC=2.7V~3.6V VCC=2.7V~3.6V Min. 0 0 36 28 36 28 25 25 25 20 5 20 15 0 3/4 3/4 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max. 12 15 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 100 36 28 200 200 Unit MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms
A.C. Characteristics
Symbol fSCK Parameter SCK Frequency
tWH
tWL tCS tCSS tCSH tSU tH tCD tHD tHO tDIS tV tLZ tHZ
Rev. 1.00
3
June 14, 2004
HT25LC512
Symbol Parameter Test Conditions Min. Typ. Max. Unit
Programming the OTP ROM fSCK tWH tWL tCS tCSS tCSH tSU tH Note: SCK Frequency SCK High Time SCK Low Time Minimum CS High Time CS Setup Time CS Hold Time Data in Setup Time Data in Hold Time For normal READ operation, dont use the 99H instruction. Output Test Load
D e v ic e Under Test
48 3 3 2 2 2 100 100
70 7.5 7.5 3/4 3/4 3/4 3/4 3/4
160 10.5 10.5 3/4 3/4 3/4 3/4 3/4
kHz ms ms ms ms ms ns ns
Test Waveforms and Measurements
2 .4 V AC D r iv in g L e v e ls 0 .4 5 V 2 .0 V 0 .8 V AC
M e a s u re m e n t Level
30pF
tR, tF< 5ns (10% to 90%)
Functional Description
Device Operation The HT25LC512 operation is controlled by instructions from the host processor. The HT25LC512 has only 3 kinds of instructions, Memory Read, Status Register read and Product ID Read. Any invalid instruction will be ignored without response from the HT25LC512. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the memory address location. While the CS pin is low, toggling the SCK pin controls the loading of the opcode and the memory address location through the SI (serial input) pin. All instructions, addresses and data are transferred with the most significant bit (MSB) first.
* Memory read
Reading the HT25LC512 via the SO (Serial Output) pin requires the following sequence. After the CS line is pulled low to select a device, the READ instruction is transmitted via the SI line followed by the byte address to read. Upon completion, any data on the SI line will be ignored. The data (D7-D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The READ instruction can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous READ instruction.
Memory read, bit sequence is shown as follows: Bit Sequential Bit data Bit Sequential Bit data Note: 0 0 16 1 0 17 2 0 18 3 0 19 4 x 20 5 0 21 6 1 22 A9 7 1 23 A8 8 x 24 A7 9 x 25 A6 10 x 26 A5 11 x 27 A4 12 x 28 A3 13 x 29 A2 14 x 30 A1 15 0 31 A0
A15 A14 A13 A12 A11 A10
x dont care
Rev. 1.00
4
June 14, 2004
HT25LC512
* Status register read
* HOLD
Status register format 0 0 1 0 2 1 3 1 4 0 5 0 6 0 7 1
Bit Sequential Bit Data
The data in the status register will always be 8CH. To read the status register, the bit sequence is shown below. After the last bit of the opcode is shifted in, the eight bits of the status register, starting with the MSB (bit 7), will be shifted out on the SO pin during the next eight clock cycles. After bit 0 of the status register has been shifted out, the sequence will repeat itself (as long as CS remains low and SCK is being toggled) starting again with bit 7.
The HOLD pin is used in conjunction with the CS pin to select the HT25LC512. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. Power-on State When power is first applied to the device, the SO pin will be in a high-impedance state, and a high-to-low transition on the CS pin will be required to start a valid instruction. The SPI mode will be automatically selected on every falling edge of CS by sampling the inactive clock state. Programming the OTP ROM Programming the OTP ROM of the HT25LC512 via the SI (Serial Input) pin requires the following sequence. After the CS line is pulled low to select a device, the programming instruction is transmitted via the SI line followed by the byte address to the program. Then the programming data are transmitted following the address. If only one byte is to be programmed, the CS line should be driven high after one byte data has been transmitted. The programming instruction can be continued since the byte address is automatically incremented and data will continue to be shifted in. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be programmed in one continuous programming instruction.
Status register read Bit sequence is shown as follows:
Bit Sequential Bit Data
0 0
1 0
2 0
3 0
4 x
5 1
6 0
7 1
Note: x dont care
* Product ID read
The RDID instruction allows the user to read the manufacturer and product ID of the device. The first byte after the instruction will be the manufacture code (1CH= HOLTEK), followed by the device code (83H for 512K OTP ROM). Product ID read, bit sequence is shown as follows: Bit Sequential Bit Data 0 0 1 0 2 0 3 1 4 x 5 1 6 0 7 1
Note: x: dont care
Programming the OTP ROM, bit sequence is shown as follows: Bit Sequential Bit Data Bit Sequential Bit Data 0 1 16 1 0 17 2 0 18 3 1 19 4 1 20 5 0 21 6 0 22 A9 7 1 23 A8 8 9 10 11 12 13 14 15
A23 A22 A21 A20 A19 A18 A17 A16 24 A7 25 A6 26 A5 27 A4 28 A3 29 A2 30 A1 31 A0
A15 A14 A13 A12 A11 A10
Rev. 1.00
5
June 14, 2004
HT25LC512
* Programming the OTP ROM timing (VPP=12.5V)
CS
0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
SCK
A22 A23 A21
SI
H ig h im p e d a n c e
A3A2A1A0D7D6D5D4D3D2D1D0 D7D6D5D4D3D2D1D0 D7D6
SO
(C o n tin u e ) CS SCK
SI SO
D7D6D5D4D3D2D1D0
Serial Interface Waveform Two different timing diagrams are shown. Waveform 1 shows the SCK signal being low when CS makes a high-to-low transition, and Waveform 2 shows the SCK signal being high when CS makes a high-to-low transition. Both waveforms show valid timing diagrams. The setup and hold times for the SI signal are referenced to the low-to-high transition on the SCK signal. Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows timing that is compatible with SPI Mode 3.
* Waveform 1 - Inactive clock polarity low
CS tC SCK tV SO H ig h im p e d a n c e tS
U SS
tC
S
tW
H
tW
L
tC
SH
tH
O
tD
IS
V a lid O u t tH
H ig h im p e d a n c e
SI
V a lid In
* Waveform 2 - Inactive clock polarity high
CS tC SCK tV SO H ig h - z tS
U SS
tC
S
tW
H
tW
L
tC
SH
tH
O
tD
IS
V a lid O u t tH
H ig h im p e d a n c e
SI
V a lid In
Rev. 1.00
6
June 14, 2004
HT25LC512
Timing Diagrams
RDSR Timing
CS 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SI
In s tr u c tio n H ig h Im p e d a n c e 7 MSB D a ta O u t 6 5 4 3 2 1 0
SO
READ Timing
CS SCK 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34 35 36 37 38
3 -B y te A d d re s s SI In s tr u c tio n
23 22 21 3 2 1 0
SO
H ig h Im p e d a n c e
7
6
5
4
3
2
1
0
HOLD Timing
CS tC
D
tC
D
SCK tH
D
tH
D
HO LD tH
Z
tL
Z
SO
RDID Timing
CS SCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
SI 0
0
0
1
x
1
0
1 D a ta O u t
7 6 5 4 3 2 1 0
SO
H ig h Im p e d a n c e M a n u fa c tu re r C o d e ( H o lte k )
D e v ic e C o d e
Rev. 1.00
7
June 14, 2004
HT25LC512
Package Information
8-pin SOP (150mil) Outline Dimensions
A 1
8
5 B 4
C
C' G D E F
H
=
Symbol A B C C D E F G H a
Dimensions in mil Min. 228 149 14 189 53 3/4 4 22 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 244 157 20 197 69 3/4 10 28 12 10
Rev. 1.00
8
June 14, 2004
HT25LC512
Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SOP 8N Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 621.5 13.0+0.5 -0.2 2.00.15 12.8+0.3 -0.2 18.20.2
Rev. 1.00
9
June 14, 2004
HT25LC512
Carrier Tape Dimensions
D
E F
P0
P1
t
W C
B0
D1
P
K0 A0
SOP 8N Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 12.0+0.3 -0.1 8.00.1 1.750.1 5.50.1 1.550.1 1.5+0.25 4.00.1 2.00.1 6.40.1 5.200.1 2.10.1 0.30.05 9.3
Rev. 1.00
10
June 14, 2004
HT25LC512
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2004 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
11
June 14, 2004

▲Up To Search▲

Price & Availability of HT25LC512

	To Download HT25LC512 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .